Spreading it thin for tiny technology
When cellular telephones, digital cameras and laptop computers first hit the market, they were mobile but not exactly lightweight. And remember the clunky “boom boxes” and Sony Walkmans that played audio cassettes? They were the portable precursors to iPods and MP3 Players. Electronic devices keep getting smaller, thanks to innovations in wafer-level packaging with thin-film technology.
Wafer-level packaging refers to fabrication on the wafer at the “wafer level” of the packaging, on-chip interconnections and test functions of an integrated circuit prior to wafer dicing (cutting) instead of the traditional process of packaging each device after wafer dicing. In other words, the entire assembly ends with fully packaged and tested integrated circuits in wafer form. The wafer is diced when the part is needed, which eliminates the steps of handling individual chips and packages. To do this, wafer-level films are needed. Xuejun Fan, an associate professor in the Department of Mechanical Engineering, has researched this area of electronics packaging extensively. He was recently awarded $174,999 for a National Science Foundation Broadening Participation Research Initiation Grants in Engineering (BRIGE) grant titled “Research and Education on Mechanical Behavior of Wafer-Level Films in Integrated Systems.”
Microelectronics devices are getting smaller and smaller, Fan explained. The silicon chips used in cell phones are just one example. “Thin-film technology is one of the critical processes to make the devices smaller,” he said. “Wafer-level film is a new process that is compatible with the wafer process. This grant intends to investigate the mechanical behavior of this new type of films.”
Fan and his team will investigate the fundamental mechanics issues associated with thin-film rupture at the reflow process in microsystems. The three-dimensional integration of micro- and nano-electronics systems requires innovations of manufacturing processes at the wafer level, Fan explained. The development of wafer-level thin film lamination is critical for the success in further function integration and lower power consumption.
A multi-physics approach, which includes new theory development and numerical implementation, will be established to investigate the mechanical behavior of wafer-level films in integrated systems. Multi-scale analysis will be developed to understand the failure processes at the nano-, micro- and macro-scales, respectively. Experiments will generate data for in-situ moisture weight gain, moisture sensitivity and reflow. Specially designed small-scale assemblies will be fabricated and tested. The test data will be used to validate the theoretical predictions and numerical simulation results.
If successful, the results of this research will directly benefit the technology development of three-dimensional micro- and nano-electronics packaging and system integration by providing an optimal manufacturing processing window. The research outcome will assist in the design of new wafer-level film materials by providing an optimal design protocol. Knowledge gained from this investigation will avoid trial-and-error experiments and will contribute to making new process development and system-level integration a reality, Fan said.
As a BRIGE grant, an education plan will be integrated to broaden the participation of engineering researchers including members from underrepresented groups and people with disabilities in the engineering disciplines. The education plan also includes outreach programs to minority undergraduate students that will promote science, technology, engineering and mathematics (STEM) careers.